Maxim Integrated MAXQ7667 - Manual (Page 150)

8.4.4.2 LIN Master Sending Protected ID and Break/Sync Example
The LIN master is now configured and ready to send the identifier and break/sync sequence to initiate communication. To have the
master send the identifier and break/sync sequence, a write to SBUF and CNT2 is required as follows.
• Load SBUF with the master protected identifier in the range 0x00–0x3F.
• Set the FBS bit (CNT2.1) to 1 to transmit a break/sync.
Once the LIN controller has been set up to transmit the identifier and break/sync, the MAXQ processor must allow sufficient time for
the data to be shifted out the transmit and break/sync serial registers shown in Figure 8-3. At the 20kbps rate, this takes a very long
time (16,000 instructions at 16MHz) relative to the MAXQ processor speed. Therefore, the MAXQ processor must wait until the
break/sync and identifier has been transmitted before the LIN controller can be set to receive.
8.4.4.3 LIN Master Polling for Transmit Complete Example
One method to wait until the data has been transmitted is to use the LIN interrupts to monitor the LIN state in the ISVEC register. The
LIN ISVEC register state 2 indicates when the protected identifier has been successfully transmitted in master mode. If a flag is set in
ISR when state 2 occurs, this flag can be tested to determine if the LIN has finished sending the break/sync. See Section 8.4.10: LIN
Interrupts for details on the interrupt.
• In the interrupt handler a flag (e.g., TX_OK = 1) is set for state 2
• Wait until TX_OK = 1 before proceeding.
This is just one method and is inefficient because the processor must wait for the transmit sequence to be complete instead of doing
other tasks. For example, the LIN message frame shown in Figure 8-1 contains the sync break, sync field, and the identifier. If we
assume a nominal sync break of 7 bits, the sync field of 6 bits, and the identifier field of 6 bits, the total is 20 bits of data. At the 20kbps
rate each bit is 50µs. Therefore, 50µs per bit multiplied by 20 bits takes approximately 1ms to shift out the LIN data. The MAXQ7667
could do another task for 1ms and then check the TX_OK flag to verify whether the LIN master is done sending the frame rather than
using the previously mentioned polling method.
8.4.4.4 LIN Master Setup to Receive Acknowledge from Slave Example
The LIN master has transmitted the break/sync and is waiting for a LIN slave to acknowledge the message and reply by sending data
and a checksum. The LIN master controller needs to be set up to receive a reply using the master’s slave task as shown in Figure 8-4.
This is done by writing the RTN (CNT1.7) bit and writing the FL (CNT1.[5:0]) bits. In this example, the RTN bit is set for receive and the
frame length is set for one byte. ( Note that the frame length is always one byte greater that the frame length bit settings.)
Additionally, the write to CNT1 must be done with one write for proper LIN state machine operation.
• Set CNT1 to 0x80 to receive and specify the frame length.
Again the MAXQ processor must wait for the LIN data to be transmitted from the slave to the master before reading the slave data in
SBUF. ISVEC is again used with a flag to indicate when the data has been received from the slave. ISVEC state 8 indicates when a
completed frame has successfully been received.
• In the interrupt handler a flag (e.g., RX_OK = 1) is set for state 8.
• Wait until RX_OK = 1 before proceeding.
• Read slave data from SBUF.
The wait loop forces the processor to wait until the data has been received and prevents the processor from doing other tasks. After
the slave data and checksum have been received, the processor can retrieve the data by reading SBUF. As was previously mentioned
in the transmit section, the wait loop can be replaced with another task, and the RX_OK flag can be tested to check if the receive is
complete.
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MAXQ7667 User’s Guide