Maxim Integrated MAXQ7667 - Manual (Page 251)

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MAXQ7667 User’s Guide
14.5.9 ADC Interrupts
The MAXQ7667 ADC can generate an interrupt when ADC data is ready.
The ADC data ready interrupt is generated when the conversion on a channel is complete and a 12-bit result is written into the SARD
register. The SAR ADC data ready (SARRDY) flag in the ASR register (ASR.0) is also set when a conversion is complete. The SARIE
bit in the AIE register (AIE.0) must be set for the interrupt to be generated. Otherwise, only the SARRDY status flag is set and the inter-
rupt is not generated.
Note: It is also required that the interrupt global enable bit (IGE) in the Interrupt and Control Register (IC) and the interrupt mask bit 5
(IM5) in the Interrupt Mask Register (IMR) are enabled for the interrupt to occur.
14.5.10 Using the ADC
The flow chart in Figure 14-11 highlights all the steps required for initializing and using the ADC.
14.5.11 Measuring ADC Reference Voltage Using AVDD as Reference
The analog ADC reference voltage can be measured by setting the ADC input multiplexer bits SARMX[2:0] to 101. This setting mea-
sures the REF (internal or external) and AVDD should be used as the reference. The AVDD can be selected as the reference by set-
ting the SARRSEL bit (SARC.5).
Under normal circumstances, a 12-bit ADC would normally work as shown by the following equation. (Note: ADC-count is rounded to
the nearest integer.)
ADC-count (SARD Register) = 4096 x input volt/reference voltage
However, by setting the SARMX and the SARRSEL bits as mentioned above, the input volt becomes the REF and the reference volt-
age becomes the AVDD. Therefore,
ADC-count = 4096 x REF/AVDD
Hence, the ADC-count from the SARD register is the digitized REF value.