Maxim Integrated MAXQ7667 - Manual (Page 57)

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MAXQ7667 User’s Guide
4.1.12 Instruction Pointer Register (IP)
Register Description: Instruction Pointer Register
Register Name: IP
Register Address: Module 0Ch, Index 00h
Bits 15 to 0: Instruction Pointer Register Bits 15:0 (IP[15:0]). This register contains the address of the next instruction to be exe-
cuted and is automatically incremented by 1 after each program fetch. Writing an address value to this register will cause program flow
to jump to that address. Reading from this register will not affect program flow.
4.1.13 Stack Pointer Register (SP)
Register Description: Stack Pointer Register
Register Name: SP
Register Address: Module 0Dh, Index 01h
Bits 15 to 4: Reserved. Read 0, write ignored.
Bits 3 to 0: Stack Pointer Register Bits 3 to 0 (SP[3:0]). These four bits indicate the current top of the hardware stack, from 0h to
Fh. This pointer is incremented after a value is pushed on the stack and decremented before a value is popped from the stack.
Bit # 15 14 13 12 11 10 9 8
Name IP15 IP14 IP13 IP12 IP11 IP10 IP9 IP8
Reset 1 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 8000h on all forms of reset.
Bit # 15 14 13 12 11 10 9 8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit # 7 6 5 4 3 2 1 0
Name — — — — SP3 SP2 SP1 SP0
Reset 0 0 0 0 1 1 1 1
Access r r r r rw rw rw rw
r = read, w = write
Note: This register is cleared to 000Fh on all forms of reset.