Maxim Integrated MAXQ7667 - Manual (Page 177)

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MAXQ7667 User’s Guide
When CKPHA is cleared (0), SS must be cycled to mark the beginning of each transfer cycle.
When CKPHA is set (1), SS can remain low between successive transfer cycles.
The MAXQ7667’s flexible clocking schemes allow peripheral devices with different transfer formats to communicate with each other,
however, the clock polarity and clock phase must be consistent for the master and selected slave device.
9.1.5 Baud-Rate Determination
The SPICK module supports a programmable shift clock rate in master mode. The master mode clock rate can be determined by the
value loaded into the SPICK register. The SPICK rate is determined by the following:
SPI master baud rate = (0.5 x SYSCLK)/(CKR[7:0]) + 1
where
SYSCLK is the frequency of the clock module. See Section 15 for more information.
CKR[7:0] are the 8-bit value loaded into the SPICK register.
In master mode, the SPICK rate cannot exceed one-half the MAXQ7667 SYSCLK.
In slave mode, the SPICK rate cannot exceed one-eighth the MAXQ7667 SYSCLK.
Writing to the SPIB during a master mode transfer cycle should not be attempted, as the cycle in progress will be corrupted and data
will be unreliable.
9.1.6 Data Format
The character length select bit (CHR) in the SPICF specifies the data length transferred to either an 8-bit or 16-bit character for a trans-
fer cycle. The SPI port state machine marks the end of a transfer cycle when the number of bits shifted in and out of the SPI shift reg-
ister equals the CHR mode. Data is always shifted out MSB first and LSB last. When the CHR bit is set (1), the SPI port is configured
for 16-bit transfer cycles, while when the CHR bit is cleared (0), the SPI port is configured for 8-bit transfer cycles. When set for 8-bit
transfer cycles, the lower byte of the read buffer contains the data, with bit 7 being the MSB of the SPI port data.
9.2 SPI Port Errors
The SPI module detects three types of SPI system errors. Each flag reports an error condition on the SPI port that causes data to be
lost or corrupted.
• Read Overrun Flag (ROVR)
• Write Collision Flag (WCOL)
• Mode Fault Flag (MODF)
9.2.1 Receive Overrun Flag (ROVR)
The receive path of the SPI port module is double buffered with the read buffer as the storage location for the first piece of data and
the shift register as the storage location for the second piece of read data. An overrun condition exists when:
• The read buffer is unread (or full) AND
• The shift register is full from the previous transfer cycle AND
• A new transfer cycle begins with the first bit of the transfer cycle shifting into the SPI shift register
The ROVR flag is set (1) at this time. The data in the read buffer remains valid in this special condition while the data in the shift reg-
ister is corrupted. Any error handling to correct this condition should:
1) Read the contents of the read buffer and handle it as valid data.
2) Clear the ROVR flag.
The assertion of the ROVR flag causes an interrupt if enabled by the ESPII bit. The ROVR bit is cleared by writing a 0 to it or by any
reset condition.