Maxim Integrated MAXQ7667 - Manual (Page 248)

_________________________________________________________________________________________________________ 14-16
MAXQ7667 User’s Guide
Table 14-5. ADC Dual- and Single-Edge Modes
ADC DUAL-
MODE
(SARDUL)
ADC CONVERSION
SOURCE
(SARS[2:0])
ADC CONVERSION
TRIGGER
ADC CONVERSION DESCRIPTION
000 (Timer 0)
001 (Timer 1)
010 (Timer 2)
100 (ADCCTL)
Rising Edge of Conversion Source
• Sets T/H into track (acquisition) mode.
• Track duration is under user control.
• If ADC is in auto shutdown, a minimum of 2.5µs (1µs for power-up and 1.5µs for
acquisition) is required.
• If ADC is not in auto shutdown, a minimum of 1.5µs acquisition delay is
required.
Falling Edge of ADCCTL
• Sets T/H into hold (conversion) mode.
• Then SAR conversion executes (13 ADC clock cycles).
101
(Inverted ADCCTL)
Falling Edge of ADCCTL
• Sets T/H into track mode.
• Track duration is under user control.
• If ADC is in auto shutdown, a minimum of 2.5µs (1µs for power-up and 1.5µs for
acquisition) is required.
• If ADC is not in auto shutdown, a minimum of 1.5µs acquisition delay is
required.
Rising Edge of ADCCTL
• Sets T/H into hold (conversion) mode.
• Then SAR conversion executes (13 ADC clock cycles).
110
(Continuous)
Write 110 to
SARS[2:0]
Write 110 to SARS[2:0]
• If in auto shutdown, logic requires 8 cycles to power up.
• Sets T/H into track mode.
• ADC control logic provides the required track duration.
• T/H placed in hold after 3 clock cycles.
• Then SAR conversion executes (13 ADC clock cycles).
Conversion continuously repeated every 16 ADC clock cycles.
1
(Dual-Edge
Mode)
111
(Start/Busy Bit)
(This mode works
exactly as the single-
edge mode.)
Write 1 to SARBY
(Start/Busy Bit)
Write 1 to SARBY (Start/Busy Bit)
• Sets T/H into track mode.
• ADC control logic provides the required track duration composed of power-up delay
(10 cycles), acquisition delay (3 cycles), and settling delay.
• If ADC is in auto shutdown, T/H placed in hold after 11 clock cycles.
• If ADC is not in auto shutdown, T/H placed in hold immediately.
• Then SAR conversion executes (13 ADC clock cycles).
000 (Timer 0)
001 (Timer 1)
010 (Timer 2)
100 (ADCCTL)
Falling Edge of Conversion Source
• Sets T/H into track mode.
• ADC control logic provides the required track duration composed of power-up
delay (10 cycles), acquisition delay (3 cycles), and settling delay.
• If ADC is in auto shutdown, T/H placed in hold after 11 clock cycles.
• If ADC is not in auto shutdown, T/H placed in hold immediately.
• Then SAR conversion executes (13 ADC clock cycles). 0
(Single-Edge
Mode)
101
(Inverted ADCCTL)
Rising Edge of ADCCTL
• Sets T/H into track mode.
• ADC control logic provides the required track duration composed of power-up
delay (10 cycles), acquisition delay (3 cycles), and settling delay.
• If ADC is in auto shutdown, T/H placed in hold after 11 clock cycles.
• If ADC is not in auto shutdown, T/H placed in hold immediately.
• Then SAR conversion executes (13 ADC clock cycles).