Maxim Integrated MAXQ7667 - Manual (Page 274)

16.2.4 Watchdog Timer Control Register (WDCN)
Register Description: Watchdog Timer Control Register
Register Name: WDCN
Register Address: Module 08h, Index 0Fh
Bit 7: Power-On Reset Flag (POR). This bit indicates whether the last reset was a power-on/brownout reset. This bit is typically inter-
rogated following a reset. It must be cleared before the next reset of any kind for software to work correctly. This bit is set following a
power-on/brownout reset and is unaffected by all other resets.
Bit 6: Watchdog Interrupt Enable (EWDI). See Section 15 for details on this bit.
Bits 5 and 4: Watchdog Timer Mode Select Bit 1 and 0 (WD[1:0]). See Section 15 for details on this bit.
Bit 3: Watchdog Interrupt Flag (WDIF). See Section 15 for details on this bit.
Bit 2: Watchdog Timer Reset Flag (WTRF). See Section 15 for details on this bit.
Bit 1: Enable Watchdog Timer Reset (EWT). See Section 15 for details on this bit.
Bit 0: Reset Watchdog Timer (RWT). See Section 15 for details on this bit.
16.3 Supply Configuration
The MAXQ7667 uses three supplies to power the internal analog, digital core, and digital I/O circuits:
• AVDD = +3.3V (with internal linear regulator enabled or through an external supply)
• DVDD = +2.5V (with internal linear regulator enabled or through an external supply)
• DVDDIO = +5V
Figure 16-2 shows the recommended supply configurations when only external power supplies are used. Bypass capacitors should
be mounted as close as possible to the MAXQ7667 to reduce noise. Figure 16-3 shows the recommended supply configuration when
the internal regulators are used to provide power to the chip. Bypass capacitors should be mounted as close as possible to the
MAXQ7667 to reduce noise.
__________________________________________________________________________________________________________ 16-8
MAXQ7667 User’s Guide
r = read, w = write
Note 1: The watchdog timer always uses the RC oscillator as the clock source.
Note 2: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset. See description for other bits.
Bit # 7 6 5 4 3 2 1 0
Name POR EWDI WD1 WD0 WDIF WTRF EWT RWT
Reset 0 0 0 0 0 0 0 0
Access r rw rw r r r rw rw