Maxim Integrated MAXQ7667 - Manual (Page 20)

2-15 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
2.2.3.8 Memory Management Unit
Memory allocation and accessing control for program and data memory can be managed by the memory management unit (MMU). A
single memory management unit option is discussed in this user’s guide, however the memory management unit implementation for
any given product depends upon the type and amount of memory addressable by the device. Users should consult the individual prod-
uct data sheet(s) and/or user’s guide supplement(s) for detailed information.
Although supporting less than the maximum addressable program and data memory segments, the MMU implementation presented
provides a high degree of programming and access control flexibility. It supports the following:
• User program memory up to 32K x 16 (up to 64K x 16 with inclusion of UPA bit).
• Utility ROM up to 8K x 16.
• Data memory SRAM up to 16K x 16.
• In-system and in-application programming of embedded EEPROM, flash, or SRAM memories.
• Access to any of the three memory areas (SRAM, code memory, utility ROM) using the data memory pointers.
• Execution from any of the three memory areas (SRAM, code memory, factory written and tested utility-ROM routines).
Given these capabilities, the following rules apply to the memory map:
• A particular memory segment cannot be simultaneously accessed as both program and data.
• The offset address is xA000h when logically mapping data memory into the program space.
• The offset for logically mapping the utility ROM into the data memory space is x8000h.
• Program memory:
- The lower half of the program memory (P0 and P1) is always accessible, starting at x0000h. ( Note: P1 is not available in the
MAXQ7667.)
- The upper half of the program memory (P2 and P3) must be activated by setting the UPA bit to 1 when accessing for code
execution, starting at x8000h. ( Note: P2 and P3 are not available in the MAXQ7667.)
- Setting the UPA bit to 1 disallows access to the utility ROM and logical data memory as program.
- Physical program memory pages (P0, P1, P2, P3) are logically mapped into data space based upon the memory segment
currently being used for execution, selection of byte/word access mode, and CDA1:0 bit settings (described in the Pseudo-
Von Neumann Memory Map and Pseudo-Von Neumann Memory Access sections). ( Note: This does not apply to the
MAXQ7667 because it has only P0.)
• Data memory
- Access can be either word or byte.
- All 16 data pointer address bits are significant in either access mode (word or byte).