Maxim Integrated MAXQ7667 - Manual (Page 260)

__________________________________________________________________________________________________________ 15-8
MAXQ7667 User’s Guide
15.2.5 Watchdog Timer Control Register (WDCN)
Register Description: Watchdog Timer Control Register
Register Name: WDCN
Register Address: Module 08h, Index 0Fh
Bit 7: Power-On Reset Flag (POR). See Section 16 for details on this bit.
Bit 6: Watchdog Interrupt Enable (EWDI). Setting this bit to 1 enables interrupt requests generated by the watchdog timer. Clearing
this bit to 0 disables the interrupt requests. This bit is cleared following a power-on reset and is unaffected by all other resets.
Bits 5 and 4: Watchdog Timer Mode Select Bit 1 and 0 (WD[1:0]). These bits are used to provide a user selection of watchdog timer
interrupt periods that determine the watchdog timer interrupt timeout when the watchdog timer is enabled. All watchdog timer reset
timeouts follow the programmed interrupt timeouts by 512 times the clock-divide ratio oscillator cycles. Table 15-1 summarizes the
watchdog timer mode select bits settings and the timeout values. Changing the WD[1:0] bit settings will reset the watchdog timer
unless the 512 RC clock reset counter has already started, in which case, changing the WD[1:0] bits will not affect the watchdog timer
or reset counter.
Bit 3: Watchdog Interrupt Flag (WDIF). This bit is set to 1 by a watchdog timeout, which indicates that a watchdog timer event has
occurred if EWT and/or EWDI are set. When the WDIF is set, EWT and EWDI determine the action to be taken. Setting this bit from 0
to 1 also activates the reset counter for the watchdog-reset timeout, which allows 512 RC cycles for the system to reset the watchdog
timer via the RWT bit. Setting this bit in software generates a watchdog interrupt if enabled and triggers the reset counter. This bit must
be cleared in software before exiting the interrupt service routine or another interrupt will be generated. The reset counter must be
cleared by RWT once started. See Table 15-1.
Table 15-1. Watchdog Timeout Settings
Bit 2: Watchdog Timer Reset Flag (WTRF). When set, this bit indicates that a watchdog timer reset has occurred. It is typically inter-
rogated to determine if a reset was caused by the watchdog timer. It is cleared by power-on reset but otherwise must be cleared by
software before the next reset of any kind to allow software to work correctly. Setting this bit by software does not generate a watch-
dog timer reset. If the EWT bit is cleared, the watchdog timer has no effect on this bit.
Bit 1: Enable Watchdog Timer Reset (EWT). Setting this bit to 1 enables the watchdog timer to reset the device; clearing this bit to
0 disables the watchdog timer reset. It has no effect on the timer itself and its ability to generate a watchdog interrupt. This bit is cleared
following a power-on reset and unaffected by all other resets.
Bit 0: Reset Watchdog Timer (RWT). Setting this bit resets the watchdog timer count. This bit must be set before the watchdog timer
expires, or a watchdog timer reset and/or interrupt will be generated if enabled. The timeout period is defined by WD1 and WD0. This
bit is always 0 when read.
EWT EWDI WDIF ACTIONS
X X 0 No interrupt has occurred.
0 0 X Watchdog disable, clock is gated off.
0 1 1 Watchdog interrupt has occurred.
1 0 1 No interrupt has been generated. Watchdog reset occurs in 512 RC clock cycles if RWT is not set.
1 1 1 Watchdog interrupt has occurred. Watchdog reset occurs in 512 RC clock cycles if RWT is not set.
Bit # 7 6 5 4 3 2 1 0
Name POR EWDI WD1 WD0 WDIF WTRF EWT RWT
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw r r rw rw
r = read, w = write
Note 1: The watchdog timer always uses the RC oscillator as the clock source.
Note 2: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset. See description for other bits.