Maxim Integrated MAXQ7667 - Manual (Page 24)

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MAXQ7667 User’s Guide
2.2.4.3 Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous. All internal interrupts are synchronous interrupts. An internal
interrupt is directly routed to the interrupt handler that can be recognized in one cycle. All external interrupts are asynchronous interrupts
by nature. When the device is not in stop mode, asynchronous interrupt sources are passed through a 3-clock sampling/glitch filter cir-
cuit before being routed to the interrupt handler. The sampling/glitch filter circuit is running on the undivided source clock (i.e., before
PMME, CD[1:0]-controlled clock divide) such that the number of system clocks required to recognize an asynchronous interrupt request
depends upon the system clock divide ratio:
• if the system clock divide ratio is 1, the interrupt request is recognized after 3 system clock
• if the system clock divide ratio is 2, the interrupt request is recognized after 2 system clock (unavailable in MAXQ7667)
• if the system clock divide ratio is 4 or greater, the interrupt request is recognized after 1 system clock (unavailable in MAXQ7667)
An interrupt request with a pulse width less than three undivided clock cycles is not recognized. Note that the granularity of interrupt
source is at module level. Synchronous interrupts and sampled asynchronous interrupts assigned to the same module product a sin-
gle interrupt to the interrupt handler.
External interrupts, when enabled, can be used as switchback sources from power management mode. There is no latency associat-
ed with the switchback because the circuit is being clocked by an undivided clock source versus the divide-by-256 system clock. For
the same reason, there is no latency for other switchback sources that do not qualify as interrupt sources.
2.2.4.4 Interrupt Prioritization by Software
All interrupt sources of the MAXQ7667 microcontroller naturally have the same priority. However, when CPU operation vectors to the pro-
grammed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to the user, as this
often depends upon the system design and application requirements. The Interrupt Mask system register provides the ability to know-
ingly block interrupts from modules considered to be of lesser priority and manually re-enable the interrupt servicing by the CPU (by set-
ting INS = 0). Using this procedure, a given interrupt service routine can continue executing, only to be interrupted by higher priority
interrupts. An example demonstrating this software prioritization is provided in Section 3.8: Handling Interrupts.
2.2.4.5 Interrupt Exception Window
An interrupt exception window is a noninterruptable execution cycle. During this cycle, the interrupt handler does not respond to any inter-
rupt requests. All interrupts that would normally be serviced during an interrupt exception window are delayed until the next execution cycle.
Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays in between.
Currently, there is a single condition in the MAXQ7667 microcontroller that causes an interrupt exception window: activation of the pre-
fix (PFX) register.
When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the prefix value to be
used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses it must always be execut-
ed back to back. Therefore, writing to the PFX register causes an interrupt exception window on the next cycle. If an interrupt occurs
during an interrupt exception window, an additional latency of one cycle in the interrupt handling will be caused as the interrupt will
not be serviced until the next cycle.
2.2.4.6 MAXQ7667 Interrupt Sources
Table 2-2 lists all possible interrupt sources for the MAXQ7667, along with their corresponding module interrupt enable bits, local inter-
rupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, will block interrupts originating in that module from being acknowledged.
When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless the interrupts have been
disabled globally).
• Each local interrupt enable bit, when cleared to 0, will disable the corresponding interrupt. When the local interrupt enable bit
is set to 1, the interrupt will be triggered whenever the interrupt flag is set to 1 (either by software or hardware).
• All interrupt flag bits cause the corresponding interrupt to trigger when the bit is set to 1. These bits are typically set by hard-
ware and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
1) Interrupts must be enabled globally by setting IGE (IC.0) to 1.
2) The module interrupt enable bit for that interrupt source’s module must be set to 1.