Maxim Integrated MAXQ7667 - Manual (Page 212)

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MAXQ7667 User’s Guide
12.3.2.3 Breakpoint Register 5 (BP5)
This register is accessible only through background mode read/write commands.
When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode,
the debug engine monitors the data memory address bus activity while the CPU is executing the user program. If an address match
is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
When (REGE = 1): This register serves as one of the two register breakpoints. A break occurs when the following two conditions are
met:
• Condition 1: The destination register address for the executed instruction matches with the specified module and index. When
used as register breakpoint, the bits BP5[3:0] are recognized as module specifier and bits BP5[8:4] are recognized as the reg-
ister index within the module. Bits BP5[15:9] are ignored.
• Condition 2: The bit pattern written to the destination register matches those bits specified for comparison by the ICDD data reg-
ister and ICDA mask register. Only those ICDD data bits with their corresponding ICDA mask bits are compared. When all bits in
the ICDA register are cleared, Condition 2 becomes a don’t care.
This register defaults to FFFFh after a power-on reset or test-logic-reset TAP state.
Register Description: Breakpoint Register 5
Register Name: BP5
Bits 15 to 0: Breakpoint Register 5 Bits 15:0 (BP5[15:0])
12.3.3 Using Breakpoints
All breakpoint registers (BP0–BP5) default to the FFFFh state on power-on reset or when the test-logic-reset TAP state is entered. The
breakpoint registers are accessible only with background mode read/write commands issued over the TAP communication link. The
breakpoint registers are not read/write accessible to the CPU.
Setting the debug-mode enable (DME) bit in the ICDC register to logic 1 enables all six breakpoint registers for breakpoint match com-
parison. The state of the break-on register enable (REGE) bit in the ICDC register determines whether the BP4 and BP5 breakpoints
should be used as data memory address breakpoints (REGE = 0) or as register breakpoints (REGE = 1).
When using the register matching breakpoints, it is important to realize that debug mode operations (e.g., read data memory, write
data memory, etc.) require the use of ICDA and ICDD for passing information between the host and MAXQ7667 ROM routines. It is
advised that these registers be saved and restored, or be reconfigured before returning to the background mode if register breakpoints
are to remain enabled.
When a breakpoint match occurs, the debug engine forces a break and the MAXQ7667 enters debug mode. If a breakpoint match
occurs on an instruction that activates the PFX register, the break is held off until the prefixed operation completes. The host can assess
whether debug mode has been entered by monitoring the status bits of the 10-bit word shifted out of the TDO pin. The status bits
change from the nondebug (00b) state associated with background mode to the debug-idle (01b) state when debug mode is entered.
Debug mode can also be manually invoked by host issuance of the debug background command.
Bit # 15 14 13 12 11 10 9 8
Name BP515 BP514 BP513 BP512 BP511 BP510 BP59 BP58
Reset 1 1 1 1 1 1 1 1
Access s s s s s s s s
Bit # 7 6 5 4 3 2 1 0
Name BP57 BP56 BP55 BP54 BP53 BP52 BP51 BP50
Reset 1 1 1 1 1 1 1 1
Access s s s s s s s s
s = special (accessible only by background mode read/write commands)