Maxim Integrated MAXQ7667 - Manual (Page 10)

2.1.3 Harvard Memory Architecture
As part of the MAXQ family, the MAXQ7667 core architecture is based on the MAXQ20 design, which implements a 16-bit internal data-
bus and ALU. Program memory, data memory, and register space on the MAXQ7667 follow the Harvard architecture model. Each type
of memory is kept separate and is accessed by a separate bus, allowing different word lengths for different types of memory. Registers
may be either 8 or 16 bits in width. Program memory is 16 bits in width to accommodate the standard MAXQ 16-bit instruction set. Data
memory is also 16 bits in width but can be accessed in 8-bit or 16-bit modes for maximum flexibility.
The MAXQ7667 includes a flexible memory management unit (MMU), which allows code to be executed from either the program flash,
the utility ROM, or the internal data SRAM. Any of these three memory spaces may also be accessed in data space at any time, with
the single restriction that whichever physical memory area is currently being used as program space cannot be read from in data
space.
2.1.4 Register Space
Since all functions in the MAXQ family are accessed through registers, common functionality is provided through a common register
set. Many of these registers provide the equivalent of higher level op codes by directly accessing the arithmetic logic unit (ALU), the
loop counter registers, and the data pointer registers. Others, such as the interrupt registers, provide common control and configura-
tion functions that are equivalent across all MAXQ microcontrollers.
The common register set, also known as the System Registers, includes the following:
• ALU access and control registers, including working accumulator registers and the processor status flags
• Two Data Pointers and a Frame Pointer for data memory access
• Autodecrementing Loop Counters for fast, compact looping
• Instruction Pointer and other branching control access points
• Stack Pointer and an access point to the 16-bit-wide dedicated hardware stack
• Interrupt vector, identification, and masking registers
The MAXQ7667 peripheral register space (modules 0 to 5) contains registers that access the following peripherals:
• Two general-purpose, 8-bit, I/O ports (P0, P1)
• LIN-compatible UART
• Serial peripheral interface (SPI)
• Hardware multiplier
• JTAG debug engine
• Three programmable Type 2 timer/counters
• Analog module
• Schedule timer
• Burst generator
• Echo receiver path
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MAXQ7667 User’s Guide