Maxim Integrated MAXQ7667 - Manual (Page 303)

17.5 Echo Reception
To facilitate implementation the following items must be addressed:
• Hardware Setup:
Receiver Clock Frequency
Voltage Reference for the Sigma-Delta ADC
External Input Coupling Capacitors
• Software Setup:
Powering Up Receiver Hardware
Echo Reception Register Configuration
Echo Reception Interrupts
17.5.1 Hardware Setup
17.5.1.1 Receiver Clock Frequency
The center frequency of the BPF tracks the burst frequency. Therefore, the burst output must be configured even if the BURST pin is
not being used. See Section 17.4: Burst Signal Generation for proper configuration of the burst output.
The highest usable frequency for the echo receive path is 100kHz (due to hardware limitations). The MAXQ7667 burst generator is
capable of higher frequencies, but for frequencies above 100kHz the echo receive path must be implemented externally. The echo
envelope can then be measured using the SAR ADC (see Section 14). Also note, from Table 17-5, that the BDIV value must be in the
09h–0Fh range because the divisor values less than 09h are not supported by the echo reception stage as indicated by the Rdivisor.
17.5.1.2 Voltage Reference for the Sigma-Delta ADC
The voltage reference for the sigma-delta ADC in the echo reception stage can either be an internal bandgap reference or an exter-
nal reference. The internal 2.5V bandgap reference can be activated by setting the BGE bit (APE.12) and the RBUFE bit (APE.14) to
1. The BGE bit enables the bandgap reference, while the RBUFE bit enables the buffer at the output of the bandgap. Bypass capac-
itors of 0.47µF should be placed from REFBG to AGND and from REF to AGND. A low ESR is required on the REF pin, therefore, it is
advised to put two capacitors in parallel.
To provide the reference from an external reference, the buffer at the output of the bandgap must be turned off, and an external refer-
ence voltage ranging between 1V and AVDD volts (analog supply voltage) can be connected to the REF pin. A bypass capacitor of
0.47µF should be placed between REF and AGND.
17.5.1.3 External Input Coupling Capacitors
For proper input biasing, the ECHOP and ECHON inputs must be capacitively coupled to the signal source (see Figure 17-2 and Figure
17-3). If the signal source is single-ended, ECHON should be connected through a capacitor to the transducer ground as close to the
transducer as possible. Circuit traces and wires from ECHON and ECHOP should be routed next to each other as much as possible.
This allows extraneous signals picked up by the traces to be rejected by the MAXQ7667’s differential input. The input coupling capac-
itors should be sized so they are large enough to pass the desired signal with little attenuation but small enough to settle quickly at
power-up and to aid in rejecting low-frequency noise. Capacitors of 10nF meet these requirements over the entire 25kHz to 100kHz
input range. It is also a good practice to place 470pF capacitors close to the MAXQ7667 from ECHOP to GND and ECHON to GND.
This attenuates high-frequency noise that might be present at the echo inputs, and prevents it from aliasing down to the base band.
The LNA also prevents aliasing by acting as a first-order LPF with its -3dB corner near 150kHz.
Proper layout techniques, including a ground plane, should be used to minimize the reception of unwanted signals on the echo inputs.
17.5.2 Software Setup
17.5.2.1 Powering Up Receiver Hardware
In addition to powering up the components necessary for the burst clock, it is also necessary to set LNAE (APE.1) and MDE (APE.2)
to 1. These bits turn on the LNA, sigma-delta modulator, sigma-delta reference buffer, and the bandgap voltage reference, respectively.
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MAXQ7667 User’s Guide