Maxim Integrated MAXQ7667 - Manual (Page 241)

14-9 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
10 divides by 8
11 divides by 16
Note that the SAR ADC accuracy is not guaranteed for SAR ADC clock frequencies exceeding 2MHz. This divider should be selected
with regard to the source clock frequency to ensure this restriction is met.
Bit 1: Crystal Enable (XTE). See Section 15 for details on this bit.
Bit 0: RC Oscillator Enable (RCE). See Section 15 for details on this bit.
14.3.6 Analog Power Enable Register (APE)
Register Description: Analog Power Enable Register
Register Name: APE
Register Address: Module 05h, Index 10h
Bits 15 and 13: Reserved. Read returns 0.
Bit 14: Reference Buffer Enable (RBUFE). The reference bandgap is enabled when set to 1 and disabled when set to 0.
Bit 12: Bandgap Enable (BGE). The reference bandgap is enabled when set to 1 and disabled when set to 0.
Bit 11: I/O Linear Regulator Power-Down (LRIOPD). See Section 16 for details on this bit.
Bit 10: Digital Linear Regulator Power-Down (LRDPD). See Section 16 for details on this bit.
Bit 9: Analog Linear Regulator Power-Down (LRAPD). See Section 16 for details on this bit.
Bit 8: I/O Voltage Brownout Detection Enable (VIBE). See Section 16 for details on this bit.
Bit 7: Digital Voltage Reset Enable (VDPE). See See Section 16 for details on this bit.
Bit 6: Digital Voltage Brownout Detection Enable (VDBE). See Section 16 for details on this bit.
Bit 5: Analog Voltage Brownout Detection Enable (VABE). See Section 16 for details on this bit.
Bit 4: SAR Enable (SARE). When set to 1, this bit enables SAR ADC. When set to 0, this bit disables SAR ADC and places it in a
leakage-only state.
Bit 3: PLL Enable (PLLE). See Section 17 for details on this bit.
Bit 2: Sigma-Delta Modulator Enable (MDE). See Section 17 for details on this bit.
Bit 1: LNA Enable (LNAE). See Section 17 for more information on this bit.
Bit 0: Bias Enable (BIASE). When set to 1, this bit enables current bias generator. When set to 0, this bit disables current bias gen-
erator and places it in a leakage-only state. BIASE is automatically set to 1 whenever LNAE, MDE, PLLE, SARE, BGE, or RBUFE are
set to 1.
Bit # 15 14 13 12 11 10 9 8
Name — RBUFE — BGE LRIOPD LRDPD LRAPD VIBE
Reset 0 0 0 0 0 0 0 0
Access r rw r rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name VDPE VDBE VABE SARE PLLE MDE LNAE BIASE
Reset 1 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
Note: APE is cleared to 0080h on all forms of reset.