15 serial address mask r, 16 bit timing register, 15 serial address mask register (uart) (saden) -16 – Maxim Integrated MAXQ7667 User Manual
Page 146: 16 bit timing register (uart) (bt) -16, Maxq7667 user’s guide, 15 serial address mask register (uart) (saden), 16 bit timing register (uart) (bt)
8.3.15 Serial Address Mask Register (UART) (SADEN)
Register Description:
Serial Address Mask Register
Register Name:
SADEN
Register Address:
Module 03h, Index 18h
Bits 7 to 0: Serial Address Mask Register 7:0 (SADEN[7:0]). In legacy UART mode, this register can be written by the host to con-
figure the address mask for the peripheral in one of the 9-bit communication modes (mode 2 or mode 3). This register serves no func-
tion if the peripheral is configured for LIN master or LIN slave mode.
8.3.16 Bit Timing Register (UART) (BT)
Register Description:
Bit Timing Register
Register Name:
BT
Register Address:
Module 03h, Index 19h
Bits 15 to 0: Bit Timing Register 15:0 (BT[15:0]). In legacy UART mode, the host initializes this register to configure the baud-rate
generator for the correct communication speed. In LIN mode, the host writes this register during system initialization to configure the
normal bit timing on the bus. Hardware updates this register with the measured bit timing whenever a break/sync sequence is detect-
ed. The host can always read this register to determine the measured bit timing for the most recent LIN frame.
In legacy UART mode this register is the phase register.
Bits 15 to 0: Phase Register 15:0 (BT[15:0]). This register is used to load and read the 16-bit value in the phase register that deter-
mines the baud rate for the serial port 0.
__________________________________________________________________________________________________________
8-16
MAXQ7667 User’s Guide
r = read, w = write
Note: SADEN is cleared to 00h on all forms of reset.
Bit #
7
6
5
4
3
2
1
0
Name
SADEN7
SADEN6
SADEN5
SADEN4
SADEN3
SADEN2
SADEN1
SADEN0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Note: BT is cleared to 0000h on all forms of reset.
Bit #
15
14
13
12
11
10
9
8
Name
BT15
BT14
BT13
BT12
BT11
BT10
BT9
BT8
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw