Maxim Integrated MAXQ7667 - Manual (Page 116)

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MAXQ7667 User’s Guide
6.7.4 Dual 8-Bit Timers
The dual 8-bit timer mode of operation is initiated by setting the T2MD bit to logic 1. When T2MD = 1, each 16-bit register associated
with the Type 2 timer is split into separate upper and lower 8-bit registers to support dual 8-bit timers. Thus, the primary 8-bit timer is
composed of T2Hx (value), T2RHx (reload), T2CHx (capture/compare), and the secondary 8-bit timer is composed of T2Lx (value),
T2RLx (reload), and T2CLx (capture/compare). There is but a single internal Type 2 timer input clock that can be sourced by either of
these two 8-bit timers. In the dual 8-bit mode of operation, both timer output clocks (from T2Lx and T2Hx) are available to internal
peripherals as required by a given product. The secondary 8-bit timer/counter has its own run control bit (TR2L) and interrupt flags
(TF2L, TC2L). Timer 1 does not support the secondary pin, therefore, it is available internally only.
• Output Enable (PWM out). The output enable bits (T2OE[1:0]) enable the respective 8-bit timer outputs to be presented on the
pins associated with the respective bits. The T2Hx timer output onto the T2Px pin is controlled by the T2OE0 bit and the T2Lx
timer output onto the T2PB pin is controlled by the T2OE1 bit. If the Type 2 timer has a single I/O pin, as in the case of timer 1,
only the T2OE0 bit is required as the secondary timer. T2Lx cannot be output to a pin and can only serve as an internal timer.
• Polarity Control. The polarity control bits (T2POL[1:0]) can be used to modify (invert) the enabled clock outputs to the pin(s).
The starting state of the enabled clock outputs (defined by T2OE[1:0]) is the logic state of T2POL[1:0] and toggles on each
compare match or overflow. The T2POL[1:0] bits are logically XORed with the timer output signal, therefore setting a given
T2POLn bit results in a high starting state. The T2POLn bit can be changed any time, however the assigned T2POLn state will
take effect on the external pin only when the corresponding T2OEn bit is changed from 0 to 1. T2POL1 is not required for a sin-
gle-pin Type 2 timer implementation.
• Gated. To use the T2Px pin as a timer input clock gate, the T2OE0 bit must be cleared to 0 and the G2EN bit must be set to 1.
When T2OE0 = 1, the G2EN bit setting has no effect. When T2OE0 is cleared to 0, the respective polarity control bit is used to
modify the polarity of the input signal to the timer. In the gated mode, the input clock to T2Hx is gated anytime that the exter-
nal signal matches the state of the T2POL0 bit. This means that the default clock gating condition is associated with the T2Px
pin being low (T2POL0 = 0). Note that the secondary 8-bit timer, T2Lx, cannot be gated. Also, since the output enables,
T2OE[1:0] apply to each individual 8-bit timer, there is no gated PWM mode available.
• Single-Shot. The single-shot bit and mode apply only to the primary 8-bit timer (T2Hx). The single-shot mode is used to auto-
mate the generation of single pulses under software control. To generate single-shot output pulses under software control, the
G2EN bit should be cleared to 0, the output enables and polarity controls should be configured as desired, and the single-shot
bit should be set to 1. Writing the single-shot bit effectively overrides the TR2 = 0 condition until the timer overflow/reload occurs.
Writing SS2 and TR2 = 1 at the same time still causes the SS2 bit to stay in effect until an overflow/reload occurs, however, the
specified PWM output continues since TR2 was also written to 1.
6.7.5 8-Bit Timer/8-Bit Capture Mode
When the CCF[1:0] bits are configured to a state other than 00b, the edge capture mode is enabled for the primary timer (T2Hx). The
secondary timer (T2Lx) always remains in the timer/compare mode and does not support any capture functionality. The capture con-
trols for the 8-bit mode are identical to those specified for the 16-bit mode, however, they apply only to the upper timer, T2Hx.
One obvious difference is that the secondary timer (T2Lx), operable only in compare mode, can be used to generate a PWM output
with valid T2OE1 and T2POL1 controls, while the primary timer is operating in capture mode. ( Note: Timer 1 does not have a secondary
pin, therefore, it is not available.)
6.7.6 8-Bit Timer/8-Bit Counter
Just as in the 16-bit mode, setting the C/T2 bit to logic 1 enables the external T2Px pin to function as a counter input. The edges that
are counted are determined by the CCF[1:0] bits. The counter mode of operation applies only to the primary timer/counter (T2Hx). In
a similar fashion to the 16-bit counter mode, when an overflow occurs, an autoreload of T2RHx occurs and the TF2 flag is set. The
TCC2 flag is also set on a compare match between the T2Hx counter and the T2CHx compare register (except for the case where
T2CHx is outside of the T2RHx to 0xFFh counting range). The secondary timer (T2Lx) always continues to operate in 8-bit compare
mode. Just as in the above split 8-bit timer/8-bit capture mode, this allows the secondary timer (T2Lx) to function in the PWM output
capacity if a T2PBx pin is provided, therefore, it is not available for timer 1. The T2POL1 control still applies to the 8-bit T2Lx PWM out-
put when T2OE1 = 1.