Maxim Integrated MAXQ7667 - Manual (Page 59)

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MAXQ7667 User’s Guide
4.1.16 Loop Counter 1 Register (LC[1])
Register Description: Loop Counter 1 Register
Register Name: LC[1]
Register Address: Module 0Dh, Index 07h
Bits 15 to 0: Loop Counter 1 Register Bits 15:0 (LC[1][15:0]). This register is used as the loop counter for the DJNZ LC[1], src oper-
ation. This operation decrements LC[1] by one and then jumps to the address specified in the instruction by src.
4.1.17 Frame Pointer Offset Register (OFFS)
Register Description: Frame Pointer Offset Register
Register Name: OFFS
Register Address: Module 0Eh, Index 03h
Bits 7 to 0: Frame Pointer Offset Register Bits 7:0 (OFFS[7:0]). This 8-bit register provides the frame pointer (FP) offset from the
base pointer (BP). The frame pointer is formed by unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset
Register (OFFS). The contents of this register can be postincremented or postdecremented when using the frame pointer for read oper-
ations and may be preincremented or pre-decremented when using the frame pointer for write operations. A carry out or borrow result-
ing from an increment/decrement operation has no effect on the Frame Pointer Base Register (BP).
Bit # 15 14 13 12 11 10 9 8
Name LC[1]15 LC[1]14 LC[1]13 LC[1]12 LC[1]11 LC[1]11 LC[1]9 LC[1]8
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name LC[1]7 LC[1]6 LC[1]5 LC[1]4 LC[1]3 LC[1]2 LC[1]1 LC[1]0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 0000h on all forms of reset.
Bit # 7 6 5 4 3 2 1 0
Name OFFS7 OFFS6 OFFS5 OFFS4 OFFS3 OFFS2 OFFS1 OFFS0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 00h on all forms of reset.