2 analog status registe, 2 analog status register (asr) -5, Maxq7667 user’s guide – Maxim Integrated MAXQ7667 User Manual
Page 257: 2 analog status register (asr)
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MAXQ7667 User’s Guide
15.2.2 Analog Status Register (ASR)
Register Description:
Analog Status Register
Register Name:
ASR
Register Address:
Module 05h, Index 08h
Bit 15: DVDDIO Brownout Comparator Output Level (VIOLVL). See Section 16 for details on this bit.
Bit 14: DVDD Brownout Comparator Output Level (DVLVL). See Section 16 for details on this bit.
Bit 13: AVDD Brownout Comparator Output Level (AVLVL). See Section 16 for details on this bit.
Bit 12: Echo Envelope Comparator Output Level (CMPLVL). See Section 17 for details on this bit.
Bits 11 to 9: Reserved. Read returns 0.
Bit 8: Crystal Oscillator Ready (XTRDY). This bit is set to 1 after the crystal oscillator has warmed up and stabilized. It is cleared
when the crystal oscillator fails or is shut down.
Bit 7: Crystal Oscillator Failure Interrupt Flag (XTI). This bit is set to 1 if the previously stable clock source (XTRDY = 1) is sourced
as the system clock (XTRC (CKCN.7) = 1) and is detected failing (XTRDY = 0). This condition causes the clock to switch over by forc-
ing RCE = 1 and XTRC (CKCN.7) = 0.
Bit 6: DVDDIO Brownout Interrupt Flag (VIBI). See Section 16 for details on this bit.
Bit 5: DVDD Brownout Interrupt Flag (VDBI). See Section 16 for details on this bit.
Bit 4: AVDD Brownout Interrupt Flag (VABI). See Section 16 for details on this bit.
Bit 3: Echo Envelope Comparator Interrupt Flag (CMPI). See Section 17 for details on this bit.
Bit 2: Echo Envelope Lowpass Filter FIFO Full Interrupt Flag (LPFFL). See Section 17 for details on this bit.
Bit 1: Echo Envelope Lowpass Filter Output Data Ready Flag (LPFRDY). See Section 17 for details on this bit.
Bit 0: SAR ADC Data Ready Flag (SARRDY). See Section 14 for details on this bit.
Bit #
15
14
13
12
11
10
9
8
Name
VIOLVL
DVLVL
AVLVL
CMPLVL
—
—
—
XTRDY
Reset
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
Bit #
7
6
5
4
3
2
1
0
Name
XTI
VIBI
VDBI
VABI
CMPI
LPFFL
LPFRDY
SARRDY
Reset
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
r = read
Note: ASR bits 3:0 are cleared to 0h on reset; bits 8:4 clear to 0h on power-on reset.