4 interrupt and control, 5 interrupt mask registe, 4 interrupt and control register (ic) -8 – Maxim Integrated MAXQ7667 User Manual
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4-8
MAXQ7667 User’s Guide
4.1.4 Interrupt and Control Register (IC)
Register Description:
Interrupt and Control Register
Register Name:
IC
Register Address:
Module 08h, Index 05h
Bits 7, 6, 4, 3, and 2: Reserved. Read 0, write ignored.
Bit 5: System Clock Gating Disable (CGDS). If this bit is set to 0 (default mode), system clock gating circuitry is active. If this bit is
set to 1, the clock gating circuitry is disabled.
Bit 1: Interrupt In Service (INS). The INS is set by hardware automatically when an interrupt is acknowledged. No further interrupts
occur as long as the INS remains set. The interrupt service routine can clear the INS bit to allow interrupt nesting. Otherwise, the INS
bit is cleared by hardware upon execution of an RETI or POPI instruction.
Bit 0: Interrupt Global Enable (IGE). If this bit is set to 1, interrupts are globally enabled, but still must be locally enabled to occur. If
this bit is set to 0, all interrupts are disabled.
4.1.5 Interrupt Mask Register (IMR)
The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module. The eighth bit, IMS, serves as a mask
for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the associated module or system
(for the case of IMS) to generate interrupt requests. Clearing the mask bit effectively disables all interrupt sources associated with that
specific module or all system interrupt sources (for the case of IMS). The interrupt mask register is intended to facilitate user-definable
interrupt prioritization.
Register Description:
Interrupt Mask Register
Register Name:
IMR
Register Address:
Module 08h, Index 06h
Bit 7: Interrupt Mask for System Modules (IMS)
Bit 6: Reserved. Read 0, write ignored.
Bits 5 to 0: Interrupt Mask for Register Module 5:0 (IM[5:0])
Bit #
7
6
5
4
3
2
1
0
Name
—
—
CGDS
—
—
—
INS
IGE
Reset
0
0
0
0
0
0
0
0
Access
r
r
rw
r
r
r
rw
rw
r = read, w = write
Note: This register is cleared to 00h on all forms of reset.
Bit #
7
6
5
4
3
2
1
0
Name
IMS
—
IM5
IM4
IM3
IM2
IM1
IM0
Reset
0
0
0
0
0
0
0
0
Access
rw
r
rw
rw
rw
rw
rw
rw
r = read, w = write
Note: This register is cleared to 00h on all forms of reset.