Maxim Integrated MAXQ7667 - Manual (Page 26)

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MAXQ7667 User’s Guide
INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG
External Interrupt Port 0 0 EX0 (EIE0.0) IE0 (EIF0.0)
External Interrupt Port 0 1 EX1 (EIE0.1) IE1 (EIF0.1)
External Interrupt Port 0 2 EX2 (EIE0.2) IE2 (EIF0.2)
External Interrupt Port 0 3 EX3 (EIE0.3) IE3 (EIF0.3)
External Interrupt Port 0 4 EX4 (EIE0.4) IE4 (EIF0.4)
External Interrupt Port 0 5 EX5 (EIE0.5) IE5 (EIF0.5)
External Interrupt Port 1 0 EX0 (EIE1.0) IE0 (EIF1.0)
External Interrupt Port 1 1 EX1 (EIE1.1) IE1 (EIF1.1)
External Interrupt Port 1 2 EX2 (EIE1.2) IE2 (EIF1.2)
External Interrupt Port 1 3 EX3 (EIE1.3) IE3 (EIF1.3)
External Interrupt Port 1 4 EX4 (EIE1.4) IE4 (EIF1.4)
External Interrupt Port 1 5 EX5 (EIE1.5) IE5 (EIF1.5)
External Interrupt Port 1 6 EX6 (EIE1.6) IE6 (EIF1.6)
External Interrupt Port 1 7
IM0 (IMR.0)
EX7 (EIE1.7) IE7 (EIF1.7)
SPI Mode Fault ESPII (SPICF.7) MODF (SPICN.3)
SPI Write Collision ESPII (SPICF.7) WCOL (SPICN.4)
SPI Receive Overrun ESPII (SPICF.7) ROVR (SPICN.5)
SPI Transfer Complete ESPII (SPICF.7) SPIC (SPICN.6)
Schedule Timer Alarm
IM1 (IMR.1)
SALIE (SCNT.7) SALMF (SCNT.6)
Timer 0—Low Compare ET2L (T2CNB0.7) T2CL (T2CNB0.0)
Timer 0—Low Overflow ET2L (T2CNB0.7) TF2L (T2CNB0.2)
Timer 0—Capture/Compare ET2 (T2NCA0.7) TCC2 (T2CNB0.1)
Timer 0—Overflow ET2 (T2NCA0.7) TF2 (T2CNB0.3)
Timer 1—Low Compare ET2L (T2CNB1.7) T2CL (T2CNB1.0)
Timer 1—Low Overflow ET2L (T2CNB1.7) TF2L (T2CNB1.2)
Timer 1—Capture/Compare ET2 (T2NCA1.7) TCC2 (T2CNB1.1)
Timer 1—Overflow
IM2 (IMR.2)
ET2 (T2NCA1.7) TF2 (T2CNB1.3)
Timer 2—Low Compare ET2L (T2CNB2.7) T2CL (T2CNB2.0)
Timer 2—Low Overflow ET2L (T2CNB2.7) TF2L (T2CNB2.2)
Timer 2—Capture/Compare ET2 (T2NCA2.7) TCC2 (T2CNB2.1)
Timer 2—Overflow ET2 (T2NCA2.7) TF2 (T2CNB2.3)
UART Mode Receive Interrupt IE (SMD.2) RI (SCON0.0)
UART Mode Transmit Interrupt IE (SMD.2) TI (SCON0.1)
LIN Mode Master or Slave Interrupt
IM3 (IMR.3)
INE (CNT0.4) INP (STA0.1)
Table 2-3. MAXQ7667 Interrupt Sources and Control Bits