Maxim Integrated MAXQ7667 - Manual (Page 17)

tion. Using Data Pointer indirectly with "++" will automatically increase the content of the active Data Pointer by 1 immediately follow-
ing the execution of read data transfer (@DP[n]++) or immediately preceding the execution of a write operation (@++DP[n]). Using
Data Pointer indirectly with "--" will decrease the content of the active Data Pointer by 1 immediately following the execution of read
data transfer (@DP[n]--) or immediately preceding the execution of a write operation (@--DP[n]).
The Frame Pointer (BP[OFFS]) is formed by 16-bit unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset
Register (OFFS). Frame Pointer can be used as a post increment/decrement source pointer by a MOVE instruction or as a pre incre-
ment/decrement destination pointer. Using Frame Pointer indirectly with "++" (@BP[++OFFS] for a write or @BP[OFFS++] for a read) will
automatically increase the content of the Frame Pointer Offset by 1 immediately before or after the execution of data transfer depending
upon whether it is used as a destination or source pointer respectively. Using Frame Pointer indirectly with "--" (@BP[--OFFS] for a write or
@BP[OFFS--] for a read) will decrease the content of the Frame Pointer Offset by 1 immediately before/after execution of data transfer
depending upon whether it is used as a destination or source pointer respectively. Note that the increment/decrement function affects the
content of the OFFS register only, while the contents of the BP register remain unaffected by the borrow/carry out from the OFFS register.
A data memory cycle contains only one system clock period to support fast internal execution. This allows read or write operations on
SRAM to be completed in one clock cycle. Data memory mapping and access control are handled by the MMU. Read/write access to
the data memory can be in word or in byte.
When using the in-circuit debugging features of the MAXQ7667, the top 32 bytes (bytes 0x7D0 to 0x7FF) of the SRAM must be reserved
for saved state storage and working space for the debugging routines in the utility ROM. If in-circuit debug will not be used, the entire
SRAM is available for application use.
2.2.3.4 Stack Memory
The MAXQ7667 provides a 16 x 16 hardware stack to support subroutine calls and system interrupts. A 16-bit wide on-chip stack is
provided by the MAXQ7667 for storage of program return addresses and general-purpose use. The stack is used automatically by the
processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced; it can also be used explicitly to
store and retrieve data by using the @SP- - source, @++SP destination, or the PUSH, POP, and POPI instructions. The POPI instruc-
tion acts identically to the POP instruction except that it additionally clears the INS bit.
The width of the stack is 16 bits to accommodate the instruction pointer size. The stack depth is 16 for the MAXQ7667. As the stack
pointer register SP is used to hold the index of the top of the stack, the maximum size of the stack allowed is defined by the number
of bits defined in the SP register (e.g., 4 bits for stack depth of 16).
On reset, the stack pointer SP initializes to the top of the stack (e.g. 0Fh for a 16-word stack). The CALL, PUSH, and interrupt vector-
ing operations increment SP and then store a value at @SP. The RET, RETI, POP, and POPI operations retrieve the value at @SP and
then decrement SP.
As with the other RAM-based modules, the stack memory is initialized to indeterminate values upon reset or power-up. Stack memory
is dedicated for stack operations only and cannot be accessed through program or data address spaces.
When using the in-circuit debugging features of the MAXQ7667, one word of the stack must be reserved to store the return location
when execution branches into the debugging routines in the utility ROM. If in-circuit debug will not be used, the entire stack is avail-
able for application use.
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MAXQ7667 User’s Guide