1 tap pins, 1 tap pins -3, Table 11-1. maxq7667 tap pins -3 – Maxim Integrated MAXQ7667 User Manual
Page 192: Maxq7667 user’s guide, Tap controller
11-3
__________________________________________________________________________________________________________
MAXQ7667 User’s Guide
11.2.1 TAP Pins
The TAP is formed by four interface signals as described in Table 11-1. The TAP signals are multiplexed with port pins P1.0, P1.1, P1.2,
and P1.3. These pins default to their JTAG TAP function on reset, which means that the MAXQ7667 device will always be ready for in-
circuit debugging or in-circuit programming following any reset.
Once an application has been loaded and starts running, the JTAG TAP port can still be used for in-circuit debugging operations. If
in-circuit debugging functionality is not needed, the P1.0, P1.1, P1.2, and P1.3 port pins can be reclaimed for application use by set-
ting the TAP (SC.7) bit to 0. This disables the JTAG TAP interface and allows the four pins to operate as normal port pins.
Table 11-1. MAXQ7667 TAP Pins
PIN
48
NAME
MULTIPLEXED WITH
PORT SIGNAL
FUNCTION
46
TDO
P1.0
JTAG Serial Test Data Output. This signal is used to serially transfer internal data to the
external host. Data is transferred least significant bit first. Data is driven out only on the falling
edge of TCK, only during TAP Shift-IR or Shift-DR states and is otherwise inactive. This pin is
weakly pulled high internally when inactive and/or when SC.7 (TAP) = 1. After power-up or a
reset this pin defaults to JTAG TDO pin.
47
TMS
P1.1
JTAG Test Mode Select Input. This signal is sampled at the rising edge of TCK and controls
movement between TAP states. TMS is weakly pulled high internally when TAP = 1. After
power-up or a reset this pin defaults to JTAG TMS pin.
48
TDI
P1.2
JTAG Serial Test Data Input. This signal is used to receive data serially transferred by the host.
Data is received least significant bit first and is sampled on the rising edge of TCK. TDI is
weakly pulled high internally when TAP = 1. After power-up or a reset this pin defaults to JTAG
TDI pin.
1
TCK
P1.3
JTAG Serial Test Clock Input. Provided by the host. When this signal is stopped at 0, storage
elements in the TAP logic retain their data indefinitely. TCK is weakly pulled high internally
when TAP = 1. After power-up or a reset this pin defaults to JTAG TCK pin.
Figure 11-1. Simplified MAXQ7667 TAP and TAP Controller
P1.0/TDO
DVDDIO
DVDDIO
DVDDIO
P1.2/TDI
WRITE
P1.3/TCK
DEBUG REGISTER
DR-SCAN
SEQUENCE
UPDATE-DR
UPDATE-DR
P1.1/TMS
SYSTEM PROGRAMMING REGISTER
READ
TO DEBUG
ENGINE
SHADOW
REGISTER
POWER-ON
RESET
BYPASS
3-BIT INSTRUCTION
SHIFT REGISTER
7
6
5
4
3
2
1
0
s1 s0
2
1
0
2
1
0
DVDDIO
IR-SCAN SEQUENCE
PARALLEL INSTRUCTION REGISTER
2
1
0
TAP CONTROLLER
IR[2:0]