Maxim Integrated MAXQ7667 - Manual (Page 281)

16.6 Reset Mode
When the MAXQ7667 is in reset mode, the enabled system clock oscillator continues running, but no instruction execution or other sys-
tem or peripheral operations occur, and all input/output pins return to default states. Once the condition that caused the reset (whether
internal or external) is removed, code execution resumes at address 8000h for all reset types.
There are four different sources that can cause the MAXQ7667 to enter reset mode. See Sections 16.4 and 16.5.1 for information on
power-on and brownout reset.
• Power-On Reset (Brownout Reset)
• Watchdog Timer Reset
• External Reset
• Internal System Reset
16.6.1 Watchdog Timer Reset
The MAXQ7667 watchdog timer is described in Section 15: Oscillator Clock Generation. The watchdog timer is a programmable hard-
ware timer that can be configured to reset the MAXQ7667 in the case of a software lockup or other unrecoverable error. Once the
watchdog is enabled in this manner, the processor must reset the watchdog periodically to avoid a reset. If the processor does not
reset the watchdog timer before it elapses, the watchdog initiates a reset state.
If the watchdog resets the MAXQ7667, it remains in reset, and holds the RESET pin low for four clock cycles. Once the reset condition
is removed, the processor begins executing program code at address 8000h. When a reset occurs due to a watchdog timeout, the
watchdog timer reset flag, WTRF (WDCN.2), is set to 1 and can only be cleared by software. User software can examine this bit fol-
lowing a reset to determine if that reset was caused by a watchdog timeout.
A watchdog reset does not affect the XTRDY bit (ASR.8) or the XTE bit (OSCC.1), so after a watchdog reset the MAXQ7667 reboots
with the same oscillator it was using before the reset.
16.6.2 External Reset
For the MAXQ7667 the RESET pin is an output as well as an input. If a reset condition is caused by an internal source (such as a POR,
watchdog, or internal reset), an output reset pulse (low level) is generated at the RESET pin.
During normal operation, the MAXQ7667 device is placed into an external reset mode by holding the RESET pin low for at least four
clock cycles. If the MAXQ7667 is in the low-power stop mode (i.e., system clock is not active), the RESET pin becomes an asynchro-
nous source, forcing the reset state immediately after being taken to logic 0. Once the MAXQ7667 enters reset mode, it remains in
reset as long as the RESET pin is held at logic 0. After the RESET pin returns to logic 1, the processor starts the internal RC oscillator
if necessary and exits the reset state within four clock cycles (Figure 16-10) and begins program execution at address 8000h.
16.6.3 Internal System Reset
The MAXQ7667 supports internal system reset capability from in-system programming mode. An internal system reset is generated
when the ROD bit (SC.2) in the SC register is set when the SPE bit (ICDF.2) in the ICDF register is also set. The bootloader software
can use this capability to initiate an internal system reset when the flash loader completes its operation. See Section 13: In-System
Programming/Bootloader for more details on in-system programming.
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MAXQ7667 User’s Guide