3 slave mode, 3 slave mode -13, Maxq7667 user’s guide – Maxim Integrated MAXQ7667 User Manual
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MAXQ7667 User’s Guide
9.1.3 Slave Mode
The MAXQ7667’s SPI port can also be configured as an SPI slave device. This is achieved by enabling the SPI port (SPIEN) with MSTM
= 0. The SCLK and SS lines are then driven by the SPI bus master. Any master device driving the SCLK on the MAXQ7667 SPI port
should limit the maximum shift rate to one-eighth the MAXQ SYSCLK rate. After the MAXQ7667 SPI port has been configured as an
SPI slave device, asserting the SS pin initiates the transfer cycle between the MAXQ to the bus master. Once SS is asserted, the STBY
flag is set and the SPI cycle is underway. STBY remains set until SS is deasserted (1). Upon completion of the transfer cycle, the SPIC
flag is set and the STBY flag is cleared. The transfer cycle is complete when the shift register count is equal to the setting of the CHR
length bit (8 or 16 bits). SS can be held low across multiple transfer cycles, when CKPHA = 0, and the MAXQ slave port loads read
data into the read buffer when the CHR setting equals the shift count.
The following steps should be taken to initialize and set up the SPI port for slave mode operation.
1)
Clear all SPI port flags (SPIC, ROVR, WCOL, MODF).
2)
Set the polarity of SS in the SPICF register.
3)
Set the SPI clocking mode (CKPOL, CKPHA) and character length (CHR) to match that of the SPI bus master configuration and
enable interrupts (if desired) in the SPICF.
4)
Set SPI slave mode, which will configure the ports to MISO (port 1.5 as output), MOSI (port 1.4 as input), SS (port 1.7 as input),
and SCLK (port 1.6 as input).
5)
Enable the SPI port in the SPICN.
6)
Write data, if available, into the SPIB in preparation for the first transfer cycle.
Figure 9-4. Slave Mode Transfer Cycle Operation
SPIB WRITE
STBY FLAG
SPIC FLAG
SPIB READ
SPICK (CKPOL = 0)
(CKPHA = 0)
SPICK (CKPOL = 1)
(CKPHA = 0)
MOSI
MISO
SS
(SET FOR ACTIVE LOW)
(NOTE 1)
NOTE 1: SPI DATA REGISTER SHOULD BE PRELOADED WITH VALID DATA OR DUMMY DATA FOR SHIFT OUT OPERATION.
NOTE 2: SPIB DATA REGISTER WRITES ARE INHIBITED WHEN STBY = 1.
(NOTE 2)
MULTIPLE
TRANSFERS
MULTIPLE
TRANSFERS
SLAVE
DISABLE
FLAG CLEARED UNDER
SOFTWARE CONTROL
TRANSFER
COMPLETE
SAMPLE EDGE
SLAVE
ENABLE
SHIFT EDGE
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
MSB