Renesas H8S/2111B - Manual (Page 57)

Rev. 1.00, 05/04, page 23 of 544
SP (ER7)
Free area
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit Bit Name
Initial
Value
R/W Description
7 T 0 R/W Trace Bit
Does not affect operation in this LSI.
6 to 3 — All 1 R Reserved
These bits are always read as 1.
2 to 0 I2
I1
I0
All 1 R/W Interrupt Mask Bits 2 to 0
Do not affect operation in this LSI.