Renesas H8S/2111B - Manual (Page 208)

Rev. 1.00, 05/04, page 174 of 544
9.5.6 Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB,
ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag.
Input capture
signal
φ
ICFA to ICFD
ICRA to ICRD
FRC
N
N
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
9.5.7 Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 9.12 shows the timing of setting the OCFA or OCFB flag.
Compare-match
signal
OCFA, OCFB
OCRA, OCRB N
FRC N N + 1
φ
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting