Renesas H8S/2111B - Manual (Page 121)

Rev. 1.00, 05/04, page 87 of 544
5.7 Address Break
5.7.1 Features
This LSI can determine the specific address prefetch by the CPU to generate an address break
interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address
break interrupt exception handling is performed.
With this function, the execution start point of a program containing a bug is detected and
execution is branched to the correcting program.
5.7.2 Block Diagram
Figure 5.8 shows a block diagram of the address break.
ABRKCR BAR
Control
logic
Comparator
Match
signal
Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.8 Address Break Block Diagram