Renesas H8S/2111B - Manual (Page 373)

Rev. 1.00, 05/04, page 339 of 544
Table 13.10 I 2 C Bus Timing (with Maximum Influence of t
Sr
/t
Sf
)
Time Indication (at Maximum Transfer Rate) [ns]
Item t
cyc
Indication
t
Sr
/t
Sf
Influence
(Max.)
I 2 C Bus
Specifi-
cation
(Min.)
φ
=
5 MHz
φ
=
8 MHz
φ
=
10 MHz
Standard mode –1000 4000 4000 4000 4000 t
SCLHO
0.5 t
SCLO
(–t
Sr
)
High-speed mode –300 600 950 950 950
Standard mode –250 4700 4750 4750 4750 t
SCLLO
0.5 t
SCLO
(–t
Sf
)
High-speed mode –250 1300 1000* 1 1000* 1 1000* 1
Standard mode –1000 4700 3800* 1 3875* 1 3900* 1 t
BUFO
0.5 t
SCLO
–1 t
cyc
(–t
Sr
)
High-speed mode –300 1300 750* 1 825* 1 850* 1
Standard mode –250 4000 4550 4625 4650 t
STAHO
0.5 t
SCLO
–1 t
cyc
(–t
Sf
)
High-speed mode –250 600 800 875 900
Standard mode –1000 4700 9000 9000 9000 t
STASO
1 t
SCLO
(–t
Sr
)
High-speed mode –300 600 2200 2200 2200
Standard mode –1000 4000 4400 4250 4200 t
STOSO
0.5 t
SCLO
+ 2 t
cyc
(–t
Sr
)
High-speed mode –300 600 1350 1200 1150
Standard mode –1000 250 3100 3325 3400 t
SDASO
(master)
1 t
SCLLO
* 3 –3 t
cyc
(–t
Sr
)
High-speed mode –300 100 400 625 700
Standard mode –1000 250 1300 2200 2500 t
SDASO
(slave)
1 t
SCLL
* 3
–12 t
cyc
* 2
(–t
Sr
)
High-speed mode –300 100 –1400* 1 –500* 1 –200* 1
Standard mode 0 0 600 375 300 t
SDAHO
3 t
cyc
High-speed mode 0 0 600 375 300
Notes: 1. Does not meet the I 2 C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
2 C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
SCLL
–
6t
cyc
).
3. Calculated using the I 2 C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).