Renesas H8S/2111B - Manual (Page 257)

Rev. 1.00, 05/04, page 223 of 544
11.2 Input/Output Pins
The WDT has the pins listed in table 11.1.
Table 11.1 Pin Configuration
Name Symbol I/O Function
Reset output pin
RESO
Output Outputs the counter overflow signal in
watchdog timer mode
External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1
prescaler counter
11.3 Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, refer to section 11.6.1,
Notes on Register Access. For details on the system control register, refer to section 3.2.2, System
Control Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
11.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is
cleared to 0.