Renesas H8S/2111B - Manual (Page 156)

Rev. 1.00, 05/04, page 122 of 544
7.9 Port 9
Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin,
subclock input pin, and system clock (
φ) output pin. P97 is an NMOS push-pull output. SDA0 is
an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following
registers.
• Port 9 data direction register (P9DDR)
• Port 9 data register (P9DR)
7.9.1 Port 9 Data Direction Register (P9DDR)
P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.
Bit Bit Name
Initial
Value
R/W Description
7 P97DDR 0 W
6 P96DDR 0 W
5 P95DDR 0 W
4 P94DDR 0 W
3 P93DDR 0 W
2 P92DDR 0 W
1 P91DDR 0 W
0 P90DDR 0 W
When the corresponding P9DDR bits are set to 1, pin
P96 functions as the
φ output pin and pins P97 and
P95 to P90 become output ports. When P9DDR bits
are cleared to 0, the corresponding pins become input
ports.
7.9.2 Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit Bit Name
Initial
Value R/W
Description
7 P97DR 0 R/W
6 P96DR Undefined* R
5 P95DR 0 R/W
4 P94DR 0 R/W
3 P93DR 0 R/W
2 P92DR 0 R/W
1 P91DR 0 R/W
0 P90DR 0 R/W
With the exception of P96, if a port 9 read is performed
while P9DDR bits are set to 1, the P9DR values are
read directly, regardless of the actual pin states. If a
port 9 read is performed while P9DDR bits are cleared
to 0, the pin states are read.
For P96, the pin state is always read.
Note: * The initial value of bit 6 is determined according to the P96 pin state.