Renesas H8S/2111B - Manual (Page 227)

Rev. 1.00, 05/04, page 193 of 544
Table 10.3 Clock Input to TCNT and Count Condition (1)
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Disables clock input
0 0 1 — 0 Increments at falling edge of internal clock
φ/8
0 0 1 — 1 Increments at falling edge of internal clock
φ/2
0 1 0 — 0 Increments at falling edge of internal clock
φ/64
0 1 0 — 1 Increments at falling edge of internal clock
φ/32
0 1 1 — 0 Increments at falling edge of internal clock
φ/1024
0 1 1 — 1 Increments at falling edge of internal clock
φ/256
TMR_0
1 0 0 — — Increments at overflow signal from
TCNT_1*
0 0 0 — — Disables clock input
0 0 1 0 — Increments at falling edge of internal clock
φ/8
0 0 1 1 — Increments at falling edge of internal clock
φ/2
0 1 0 0 — Increments at falling edge of internal clock
φ/64
0 1 0 1 — Increments at falling edge of internal clock
φ/128
0 1 1 0 — Increments at falling edge of internal clock
φ/1024
0 1 1 1 — Increments at falling edge of internal clock
φ/2048
TMR_1
1 0 0 — — Increments at compare-match A from
TCNT_0*
Common 1 0 1 — — Increments at rising edge of external clock
1 1 0 — — Increments at falling edge of external clock
1 1 1 — — Increments at both rising and falling edges
of external clock
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.