Renesas H8S/2111B - Manual (Page 104)

Rev. 1.00, 05/04, page 70 of 544
Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name ICRA ICRB ICRC
7 ICRn7 IRQ0 — —
6 ICRn6 IRQ1 FRT SCI_1
5 ICRn5 IRQ2, IRQ3 — —
4 ICRn4 IRQ4, IRQ5 — IIC_0
3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1
2 ICRn2 — TMR_1 TMR_A, TMR_B
1 ICRn1 WDT_0 TMR_X, TMR_Y LPC
0 ICRn0 WDT_1 Keyboard buffer controller —
[Legend]
n:
A to C
:
Reserved. The write value should always be 0.
5.3.2 Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name
Initial
Value R/W Description
7 CMF 0 R Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
6
to
1 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
0 BIE 0 R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled