Renesas H8S/2111B - Manual (Page 346)

Rev. 1.00, 05/04, page 312 of 544
12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
SDA
(master output)
SDA
(slave output)
2 1
R/W
4 3 6 5 8 7 1 2 9
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
ICDRE
IRTR
ICDRT
Note:* Data write
in ICDR
prohibited
SCL
(master output)
Start condition generation
Slave address Data 1
Data 1
[9] ICDR write [9] IRIC clear [6] ICDR write [6] IRIC clear
[4] BBSY set to 1
SCP cleared to 0
(start condition issuance)
User processing
Interrupt
request Interrupt
request
Address + R/ W
IRIC
[7]
[5]
ICDRS Data 1 Address + R/ W
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)