Renesas H8S/2111B - Manual (Page 258)

Rev. 1.00, 05/04, page 224 of 544
11.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)* 1 Overflow Flag
Indicates that TCNT has overflowed (changes from
H'FF to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1* 2 , then 0 is
written to OVF
• When 0 is written to TME
6 WT/
IT
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4 — 0 R/(W) Reserved
The initial value should not be modified.
3 RST/
NMI 0
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested