Renesas H8S/2111B User Manual
Page 358
Rev. 1.00, 05/04, page 324 of 544
SDA
(master output)
SDA
(slave output)
2
1
2
1
4
3
6
5
8
7
9
Bit 7
Bit 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
Address
+R/
W
Address
+R/
W
Undefined value
[8] IRIC clear
[10] ICDR read (dummy read)
User processing
2
1
2
1
4
3
6
5
8
7
9
SCL
(Pin waveform)
Start condition generation
Slave address
Data 1
[6]
A
R/
W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 13.18 Example of Slave Receive Mode Operation Timing (1)
(MLS = 0, HNDS= 1)
SDA
(master output)
SDA
(slave output)
2
1
4
3
6
5
8
7
9
8
9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
SCL
(slave output)
[8] IRIC clear
[12] IRIC clear
[9] Set ACKB=1
[5] ICDR read (Data (n-1))
[10] ICDR read
(Data (n))
User processing
Data (n)
Data (n-1)
Data (n-2)
[6] [6]
[11]
A
A
Stop condition generation
[7] SCL is fixed low until ICDR is read
[7] SCL is fixed low until ICDR is read
Data (n-1)
Data (n)
Data (n)
[8] IRIC clear
Data (n-1)
Figure 13.19 Example of Slave Receive Mode Operation Timing (2)
(MLS = 0, HNDS= 1)