Renesas H8S/2111B - Manual (Page 465)

ROMF360A_010020040200
Rev. 1.00, 05/04, page 431 of 544
Section 18 ROM
This LSI has an on-chip ROM (flash memory). The features of the flash memory are summarized
below.
A block diagram of the flash memory is shown in figure 18.1.
18.1 Features
• Size
Product Classification ROM Capacitance ROM Address
H8S/2111B 64 Kbytes H'000000 to H'00FFFF (mode 2)
H'0000 to H'DFFF (mode 3)
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
The flash memory is configured as follows:
 8 Kbytes × 2 blocks, 16 Kbytes × 1 block, 28 Kbytes × 1 block, and 1 Kbyte × 4 blocks
To erase the entire flash memory, each block must be erased in turn.
• Programming/erase time
It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 µs (typ.) per 1 byte.
Erasing one block takes 100 ms (typ.).
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• Two flash memory on-board programming modes
 Boot mode
 User program mode
On-board programming/erasing can be done in boot mode in which the boot program built into
the chip is started for erase or programming of the entire flash memory. In user program mode,
individual blocks can be erased or programmed.
• Automatic bit rate adjustment
With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the
transfer bit rate of the host.
• Programming/erasing protection
Sets protection against flash memory programming/erasing via hardware, software, or error
protection.