Renesas H8S/2111B - Manual (Page 120)

Rev. 1.00, 05/04, page 86 of 544
5.6.4 Interrupt Response Times
Table 5.5 shows interrupt response times
− the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.5 are explained in table 5.6.
Table 5.5 Interrupt Response Times
No. Execution Status Normal Mode Advanced Mode
1 Interrupt priority determination* 1 3
2 Number of wait states until executing
instruction ends*
2
1 to (19 + 2·S I )
3 PC, CCR stack save 2·S K 2·S K
4 Vector fetch S
I
2·S
I
5 Instruction fetch* 3 2·S I
6 Internal processing* 4 2
Total (using on-chip memory) 11 to 31 12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.6 Number of States in Interrupt Handling Routine Execution Status
Object of Access
Symbol Internal Memory
Instruction fetch S I
Branch address read S
J
Stack manipulation S K
1