Renesas H8S/2111B - Manual (Page 102)

Rev. 1.00, 05/04, page 68 of 544
SYSCR
NMI input
IRQ input
Internal
interrupt request
WOVI0 to IBFI3
NMIEG
INTM1, INTM0
NMI input
IRQ input
ISR
ISCR IER
ICR
Interrupt controller
Priority check
Interrupt
request
Vector number
I, UI
CCR
CPU
ICR:
ISCR:
IER:
ISR: Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register KMIMR:
WUEMR:
SYSCR: Keyboard matrix interrupt mask register
Wake-up event interrupt mask register
System control register
[Legend]
KIN and WUE
input
KMIMR WUEMR
KIN input
WUE input
Figure 5.1 Block Diagram of Interrupt Controller
5.2 Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Symbol I/O Function
NMI Input Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ7 to IRQ0
Input Maskable external interrupts
Rising edge, falling edge, both edges, or level sensing,
can be selected individually for each pin.
KIN15 to KIN0
Input Maskable external interrupts
Falling edge or level sensing can be selected.
WUE7 to WUE0
Input Maskable external interrupts
Falling edge or level sensing can be selected.