Renesas H8S/2111B User Manual
Page 16
Rev. 1.00, 05/04, page xvi of xxxiv
11.6.5
System Reset by
RESO Signal ............................................................................ 233
11.6.6
Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 233
Section 12 Serial Communication Interface (SCI)............................................ 235
12.1
Features............................................................................................................................. 235
12.2
Input/Output Pins.............................................................................................................. 236
12.3
Register Descriptions ........................................................................................................ 237
12.3.1
Receive Shift Register (RSR) .............................................................................. 237
12.3.2
Receive Data Register (RDR).............................................................................. 237
12.3.3
Transmit Data Register (TDR)............................................................................. 237
12.3.4
Transmit Shift Register (TSR) ............................................................................. 238
12.3.5
Serial Mode Register (SMR) ............................................................................... 238
12.3.6
Serial Control Register (SCR) ............................................................................. 239
12.3.7
Serial Status Register (SSR) ................................................................................ 241
12.3.8
Serial Interface Mode Register (SCMR).............................................................. 243
12.3.9
Bit Rate Register (BRR) ...................................................................................... 244
12.3.10
Serial Pin Select Register (SPSR)........................................................................ 249
12.4
Operation in Asynchronous Mode .................................................................................... 249
12.4.1
Data Transfer Format........................................................................................... 250
12.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 251
12.4.3
Clock.................................................................................................................... 251
12.4.4
SCI Initialization (Asynchronous Mode)............................................................. 253
12.4.5
Data Transmission (Asynchronous Mode) .......................................................... 254
12.4.6
Serial Data Reception (Asynchronous Mode) ..................................................... 256
12.5
Multiprocessor Communication Function......................................................................... 259
12.5.1
Multiprocessor Serial Data Transmission ............................................................ 260
12.5.2
Multiprocessor Serial Data Reception ................................................................. 261
12.6
Operation in Clocked Synchronous Mode ........................................................................ 264
12.6.1
Clock.................................................................................................................... 264
12.6.2
SCI Initialization (Clocked Synchronous Mode)................................................. 265
12.6.3
Serial Data Transmission (Clocked Synchronous Mode) .................................... 266
12.6.4
Serial Data Reception (Clocked Synchronous Mode) ......................................... 268
12.6.5
Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 269
12.7
Interrupt Sources............................................................................................................... 271
12.8
Usage Notes ...................................................................................................................... 272
12.8.1
Module Stop Mode Setting .................................................................................. 272
12.8.2
Break Detection and Processing .......................................................................... 272
12.8.3
Mark State and Break Detection .......................................................................... 272
12.8.4
Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 272
12.8.5
Relation between Writing to TDR and TDRE Flag ............................................. 272