4 operation, 1 pulse output – Renesas H8S/2111B User Manual

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Rev. 1.00, 05/04, page 169 of 544

9.4 Operation

9.4.1 Pulse

Output

Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When
a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits
are inverted by software.

H'FFFF

OCRA

OCRB

H'0000

FTOA

FTOB

Counter clear

FRC

Figure 9.2 Example of Pulse Output

This manual is related to the following products:

HD64F2111B