Renesas H8S/2111B - Manual (Page 560)

Rev. 1.00, 05/04, page 526 of 544
Table 22.10 LPC Module Timing
Conditions: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V,
φ = 4 MHz to maximum operating frequency,
T
a
= –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Input clock cycle t
Lcyc
30 — —
Input clock pulse width (H) t
LCKH
11 — —
Input clock pulse width (L) t
LCKL
11 — —
Transmit signal delay time t
TXD
2 — 11
Transmit signal floating
delay time t
OFF
— — 28
Receive signal setup time t
RXS
7 — —
LPC
Receive signal hold time t
RXH
0 — —
ns Figure 22.23
22.4 A/D Conversion Characteristics
Tables 22.11 list the A/D conversion characteristics.
Table 22.11 A/D Conversion Characteristics (AN5 to AN0 Input: 134/266-State Conversion)
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, AV
ref
= 3.0 V to AV
CC
,
V
CC
B = 3.0 V to 5.5 V, V
SS
= AV
SS
= 0 V,
φ = 4 MHz to maximum operating frequency, T
a
= –20 to +75°C
Condition
10 MHz
Item Min. Typ. Max. Unit
Resolution 10 bits
Conversion time — — 13.4 µs
Analog input capacitance — — 20 pF
Permissible signal-source impedance — — 5 k
Ω
Nonlinearity error — — ±7.0 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB