Renesas H8S/2111B - Manual (Page 35)

Rev. 1.00, 05/04, page 1 of 544
Section 1 Overview
1.1 Features
• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
8-bit PWM timer (PWM)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
I 2 C bus interface (IIC)
Keyboard buffer controller
Host interface (LPC)
10-bit A/D converter
Clock pulse generator
• On-chip memory
ROM Model ROM RAM Remarks
F-ZTAT Version HD64F2111BVB* 64 Kbytes 2 Kbytes
HD64F2111BVC* 64 Kbytes 3 Kbytes
Note: * 3-V version product
• General I/O ports
I/O pins: 114
Input-only pins: 8
• Supports various power-down states
• Compact package
Product Package Code Body Size Pin Pitch
H8S/2111B TQFP-144 TFP-144 18.0
× 18.0 mm 0.4 mm