Renesas H8S/2111B - Manual (Page 387)

Rev. 1.00, 05/04, page 353 of 544
14.3.2 Keyboard Control Register L (KBCRL)
KBCRL enables the receive counter count and controls the keyboard buffer controller pin output.
Bit Bit Name
Initial
Value R/W Description
7 KBE 0 R/W Keyboard Enable
Enables or disables loading of receive data into KBBR.
0: Loading of receive data into KBBR is disabled
1: Loading of receive data into KBBR is enabled
6 KCLKO 1 R/W Keyboard Clock Out
Controls KBC clock I/O pin output.
0: KBC clock I/O pin is low
1: KBC clock I/O pin is high
5 KDO 1 R/W Keyboard Data Out
Controls KBC data I/O pin output.
0: KBC data I/O pin is low
1: KBC data I/O pin is high
4 — 1 — Reserved
This bit is always read as 1 and cannot be modified.
3
2
1
0
RXCR3
RXCR2
RXCR1
RXCR0
0
0
0
0
R
R
R
R
Receive Counter
These bits indicate the received data bit. Their value is
incremented on the fall of KCLK. These bits cannot be
modified.
The receive counter is initialized to 0000 by a reset and
when 0 is written in KBE. Its value returns to 0000 after
a stop bit is received.
0000: —
0001: Start bit
0010: KB0
0011: KB1
0100: KB2
0101: KB3
0110: KB4
0111: KB5
1000: KB6
1001: KB7
1010: Parity bit
1011: —
11- - : —