Renesas H8S/2111B - Manual (Page 182)

Rev. 1.00, 05/04, page 148 of 544
8.2 Input/Output Pins
Table 8.1 shows the PWM output pins.
Table 8.1 Pin Configuration
Name Abbreviation I/O Function
PWM output 7 to 0 PW7 to PW0 Output PWM timer pulse output 7 to 0
8.3 Register Descriptions
The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control
register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see
section 3.2.3, Serial Timer Control Register (STCR).
• PWM register select (PWSL)
• PWM data registers 7 to 0 (PWDR7 to PWDR0)
• PWM data polarity register A (PWDPRA)
• PWM output enable register A (PWOERA)
• Peripheral clock select register (PCSR)