Renesas H8S/2111B - Manual (Page 269)

SCI0022C_000020020800
Rev. 1.00, 05/04, page 235 of 544
Section 12 Serial Communication Interface (SCI)
This LSI has a serial communication interface (SCI). The SCI can handle both asynchronous and
clocked synchronous serial communication. Asynchronous serial data communication can be
carried out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function) in asynchronous mode.
12.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• The on-chip baud rate generator allows any bit rate to be selected
An external clock can be selected as a transfer clock source.
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests.
Asynchronous Mode:
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
Clocked Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
• Serial data communication with other LSIs that have the clock synchronized communication
function
A block diagram of the SCI is shown in figure 12.1.