Renesas H8S/2111B - Manual (Page 260)

Rev. 1.00, 05/04, page 226 of 544
Bit Bit Name
Initial
Value R/W Description
4 PSS 0 R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of
φ–based prescaler (PSM)
1: Counts the divided cycle of
φSUB–based prescaler
(PSS)
3 RST/
NMI 0
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to TCNT. The
overflow cycle for
φ = 10 MHz and φSUB = 32.768 kHz is
enclosed in parentheses.
When PSS = 0:
000:
φ/2 (frequency: 51.2 µs)
001:
φ/64 (frequency: 1.64 ms)
010:
φ/128 (frequency: 3.28 ms)
011:
φ/512 (frequency: 13.1 ms)
100:
φ/2048 (frequency: 52.4 ms)
101:
φ/8192 (frequency: 209.7 ms)
110:
φ/32768 (frequency: 0.84 s)
111:
φ/131072 (frequency: 3.36 s)
When PSS = 1:
000:
φSUB/2 (cycle: 15.6 ms)
001:
φSUB/4 (cycle: 31.3 ms)
010:
φSUB/8 (cycle: 62.5 ms)
011:
φSUB/16 (cycle: 125 ms)
100:
φSUB/32 (cycle: 250 ms)
101:
φSUB/64 (cycle: 500 ms)
110:
φSUB/128 (cycle: 1 s)
111:
φ/256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.