Renesas HD64F2111B Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for HD64F2111B Renesas
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 582 |
| Size: | 3.82 MB |
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Document Outline
- Cover
- Keep safety first in your circuit designs!
- Notes regarding these materials
- General Precautions on Handling of Product
- Configuration of This Manual
- Preface
- Contents
- Figures
- Tables
- Section 1 Overview
- Section 2 CPU
- 2.1 Features
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
- 2.5 Data Formats
- 2.6 Instruction Set
- 2.7 Addressing Modes and Effective Address Calculation
- 2.7.1 Register Direct—Rn
- 2.7.2 Register Indirect—@ERn
- 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
- 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
- 2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
- 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
- 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
- 2.7.8 Memory Indirect—@@aa:8
- 2.7.9 Effective Address Calculation
- 2.8 Processing States
- 2.9 Usage Notes
- Section 3 MCU Operating Modes
- Section 4 Exception Handling
- Section 5 Interrupt Controller
- 5.1 Features
- 5.2 Input/Output Pins
- 5.3 Register Descriptions
- 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)
- 5.3.2 Address Break Control Register (ABRKCR)
- 5.3.3 Break Address Registers A to C (BARA to BARC)
- 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)
- 5.3.5 IRQ Enable Register (IER)
- 5.3.6 IRQ Status Register (ISR)
- 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB)
- 5.4 Interrupt Sources
- 5.5 Interrupt Exception Handling Vector Table
- 5.6 Interrupt Control Modes and Interrupt Operation
- 5.7 Address Break
- 5.8 Usage Notes
- Section 6 Bus Controller (BSC)
- Section 7 I/O Ports
- 7.1 Port 1
- 7.2 Port 2
- 7.3 Port 3
- 7.4 Port 4
- 7.5 Port 5
- 7.6 Port 6
- 7.7 Port 7
- 7.8 Port 8
- 7.9 Port 9
- 7.10 Port A
- 7.11 Port B
- 7.12 Ports C, D
- 7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR)
- 7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR)
- 7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)
- 7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)
- 7.12.5 Pin Functions
- 7.12.6 Input Pull-Up MOS in Ports C and D
- 7.13 Ports E, F
- 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR)
- 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR)
- 7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)
- 7.13.4 Pin Functions
- 7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)
- 7.13.6 Pin Functions
- 7.13.7 Input Pull-Up MOS in Ports E and F
- 7.14 Port G
- Section 8 8-Bit PWM Timer (PWM)
- Section 9 16-Bit Free-Running Timer (FRT)
- 9.1 Features
- 9.2 Input/Output Pins
- 9.3 Register Descriptions
- 9.3.1 Free-Running Counter (FRC)
- 9.3.2 Output Compare Registers A and B (OCRA, OCRB)
- 9.3.3 Input Capture Registers A to D (ICRA to ICRD)
- 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
- 9.3.5 Output Compare Register DM (OCRDM)
- 9.3.6 Timer Interrupt Enable Register (TIER)
- 9.3.7 Timer Control/Status Register (TCSR)
- 9.3.8 Timer Control Register (TCR)
- 9.3.9 Timer Output Compare Control Register (TOCR)
- 9.4 Operation
- 9.5 Operation Timing
- 9.5.1 FRC Increment Timing
- 9.5.2 Output Compare Output Timing
- 9.5.3 FRC Clear Timing
- 9.5.4 Input Capture Input Timing
- 9.5.5 Buffered Input Capture Input Timing
- 9.5.6 Timing of Input Capture Flag (ICF) Setting
- 9.5.7 Timing of Output Compare Flag (OCF) setting
- 9.5.8 Timing of FRC Overflow Flag Setting
- 9.5.9 Automatic Addition Timing
- 9.5.10 Mask Signal Generation Timing
- 9.6 Interrupt Sources
- 9.7 Usage Notes
- Section 10 8-Bit Timer (TMR)
- 10.1 Features
- 10.2 Input/Output Pins
- 10.3 Register Descriptions
- 10.3.1 Timer Counter (TCNT)
- 10.3.2 Time Constant Register A (TCORA)
- 10.3.3 Time Constant Register B (TCORB)
- 10.3.4 Timer Control Register (TCR)
- 10.3.5 Timer Control/Status Register (TCSR)
- 10.3.6 Time Constant Register (TCORC)
- 10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)
- 10.3.8 Timer Input Select Register (TISR and TISR_B)
- 10.3.9 Timer Connection Register I (TCONRI)
- 10.3.10 Timer Connection Register S (TCONRS)
- 10.3.11 Timer XY Control Register (TCRXY)
- 10.3.12 Timer AB Control Register (TCRAB)
- 10.4 Operation
- 10.5 Operation Timing
- 10.6 TMR_0 and TMR_1 Cascaded Connection
- 10.7 TMR_Y and TMR_X Cascaded Connection
- 10.8 TMR_B and TMR_A Cascaded Connection
- 10.9 Interrupt Sources
- 10.10 Usage Notes
- 10.10.1 Conflict between TCNT Write and Counter Clear
- 10.10.2 Conflict between TCNT Write and Count-Up
- 10.10.3 Conflict between TCOR Write and Compare-Match
- 10.10.4 Conflict between Compare-Matches A and B
- 10.10.5 Switching of Internal Clocks and TCNT Operation
- 10.10.6 Mode Setting with Cascaded Connection
- 10.10.7 Module Stop Mode Setting
- Section 11 Watchdog Timer (WDT)
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Register Descriptions
- 11.4 Operation
- 11.5 Interrupt Sources
- 11.6 Usage Notes
- 11.6.1 Notes on Register Access
- 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment
- 11.6.3 Changing Values of CKS2 to CKS0 Bits
- 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
- 11.6.5 System Reset by RESO Signal
- 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes
- Section 12 Serial Communication Interface (SCI)
- 12.1 Features
- 12.2 Input/Output Pins
- 12.3 Register Descriptions
- 12.3.1 Receive Shift Register (RSR)
- 12.3.2 Receive Data Register (RDR)
- 12.3.3 Transmit Data Register (TDR)
- 12.3.4 Transmit Shift Register (TSR)
- 12.3.5 Serial Mode Register (SMR)
- 12.3.6 Serial Control Register (SCR)
- 12.3.7 Serial Status Register (SSR)
- 12.3.8 Serial Interface Mode Register (SCMR)
- 12.3.9 Bit Rate Register (BRR)
- 12.3.10 Serial Pin Select Register (SPSR)
- 12.4 Operation in Asynchronous Mode
- 12.5 Multiprocessor Communication Function
- 12.6 Operation in Clocked Synchronous Mode
- 12.7 Interrupt Sources
- 12.8 Usage Notes
- 12.8.1 Module Stop Mode Setting
- 12.8.2 Break Detection and Processing
- 12.8.3 Mark State and Break Detection
- 12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
- 12.8.5 Relation between Writing to TDR and TDRE Flag
- 12.8.6 SCI Operations during Mode Transitions
- 12.8.7 Switching from SCK Pins to Port Pins
- Section 13 I2C Bus Interface (IIC)
- 13.1 Features
- 13.2 Input/Output Pins
- 13.3 Register Descriptions
- 13.3.1 I2C Bus Data Register (ICDR)
- 13.3.2 Slave Address Register (SAR)
- 13.3.3 Second Slave Address Register (SARX)
- 13.3.4 I2C Bus Mode Register (ICMR)
- 13.3.5 I2C Bus Control Register (ICCR)
- 13.3.6 I2C Bus Status Register (ICSR)
- 13.3.7 DDC Switch Register (DDCSWR)
- 13.3.8 I2C Bus Extended Control Register (ICXR)
- 13.3.9 Port G Control Register (PGCTL)
- 13.4 Operation
- 13.5 Interrupt Sources
- 13.6 Usage Notes
- Section 14 Keyboard Buffer Controller
- Section 15 Host Interface (LPC)
- 15.1 Features
- 15.2 Input/Output Pins
- 15.3 Register Descriptions
- 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)
- 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
- 15.3.3 LPC Channel 3 Address Register (LADR3)
- 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)
- 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)
- 15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
- 15.3.7 Status Registers 1 to 3 (STR1 to STR3)
- 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
- 15.3.9 Host Interface Select Register (HISEL)
- 15.4 Operation
- 15.5 Interrupt Sources
- 15.6 Usage Notes
- Section 16 A/D Converter
- Section 17 RAM
- Section 18 ROM
- 18.1 Features
- 18.2 Mode Transitions
- 18.3 Block Configuration
- 18.4 Input/Output Pins
- 18.5 Register Descriptions
- 18.6 Operating Modes
- 18.7 On-Board Programming Modes
- 18.8 Flash Memory Programming/Erasing
- 18.9 Program/Erase Protection
- 18.10 Interrupts during Flash Memory Programming/Erasing
- 18.11 Programmer Mode
- 18.12 Usage Notes
- Section 19 Clock Pulse Generator
- Section 20 Power-Down Modes
- Section 21 List of Registers
- Section 22 Electrical Characteristics
- Appendix
- Index
- Colphon
- Address List
- Back Cover