Renesas H8S/2111B - Manual (Page 347)

Rev. 1.00, 05/04, page 313 of 544
SDA
(master output)
SDA
(slave output)
2 1 4 3 6 5 8 7 9 8 9
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0
ICDRE
IRTR
ICDR
SCL
(master output)
Start condition issuance
Data 2
[9] ICDR write [9] IRIC clear
[12] IRIC clear
[11] ACKB read [12] Set BBSY = 1and
SCP = 0
(Stop condition issuance)
IRIC
A
[10] [7] Data 1
Data 1 Data 2
User processing
Figure 13.9 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)