Renesas H8S/2111B - Manual (Page 115)

Rev. 1.00, 05/04, page 81 of 544
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program excution state
Interrupt generated?
NMI
An interrupt with interrupt
control level 1?
IRQ0
IRQ1
IBFI3
IRQ0
IRQ1
IBFI3
I = 0
Save PC and CCR
I 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0