Renesas H8S/2111B - Manual (Page 429)

Rev. 1.00, 05/04, page 395 of 544
15.3.9 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt
request signal of each frame.
R/W
Bit Bit Name Initial Value Slave Host Description
7 SELSTR3 0 W STR3 Register Function Select 3
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. See
description on STR3 in section 15.3.7, Status
Registers 1 to 3 (STR1 to STR3), for details.
0: Bits 7 to 4 in STR3 are status bits of the host
interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 are status bits of the host
interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are user bits.
6
5
4
3
2
1
0
SELIRQ11
SELIRQ10
SELIRQ9
SELIRQ6
SELSMI
SELIRQ12
SELIRQ1
0
0
0
0
0
1
1
W
W
W
W
W
W
W
—
—
—
—
—
—
—
SERIRQ Output Select
Selects the pin output status of host interrupt
requests (HIRQ11, HIRQ10, HIRQ9, HIRQ6, SMI,
HIRQ12, and HIRQ1) of the LPC.
0: [When host interrupt request is cleared]
SERIRQ pin output is in the high-impedance
state.
[When host interrupt request is set]
SERIRQ pin output is 0.
1: [When host interrupt request is cleared]
SERIRQ pin output is 0.
[When host interrupt request is set]
SERIRQ pin output is in the high-impedance
state.