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Renesas H8S/2111B User Manual

Page 361

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Rev. 1.00, 05/04, page 327 of 544

SDA

(master output)

SDA

(slave output)

2

1

4

3

2

1

4

3

6

5

8

7

9

Bit 7

Bit 6

Bit 7

Bit 6 Bit 5

Bit 4

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

ICDRF

ICDRS

ICDRR

IRIC

SCL

(master output)

Start condition issuance

Address+R/

W

Data 1

Address+R/

W

[8] IRIC clear

[10] ICDR read

User processing

Slave address

[6]

[7]

A

R/

W

Data 1

Figure 13.21 Example of Slave Receive Mode Operation Timing (1)

(MLS = ACKB = 0, HNDS = 0)

Start condition detection

SDA

(master output)

SDA

(slave output)

2

1

4

3

6

5

2

1

4

3

6

5

8

7

9

8

7

9

8

9

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 1 Bit 0

ICDRF

ICDRS

ICDRR

IRIC

SCL

(master output)

[9] Set ACKB = 1

[13] IRIC clear

[10] ICDR read
(Data n-2)

[10] ICDR read
(Data n-1)

[13] IRIC clear

[9] Wait for one frame

User processing

Bit 7

Bit 0

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Data n

Data n-1

Data n-1

Data n-1

Data n-2

Data n-2

Data n

Data n

Data n-2

[11]

[11]

[11]

A

A

A

[13] IRIC clear

[14] ICDR read
(Data n)

[15] IRIC clear

[11]

Figure 13.22 Example of Slave Receive Mode Operation Timing (2)

(MLS = ACKB = 0, HNDS = 0)

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